(1) Field of the Invention
The present invention relates to a method of fabricating a dynamic random access memory having an increased capacitance capacitor having an E-shaped storage node.
(2) Description of the Prior Art
In recent years there has been a dramatic increase in the packing density of DRAMs. Large DRAM devices are normally silicon based, and each cell typically embodies a single MOS field effect transistor with its source connected to a storage capacitor. This large integration of DRAMs has been accomplished by a reduction in individual cell size. However, the reduction in cell size results in a decrease in storage capacitance leading to reliability drawbacks, such as a lowering of source/drain ratio and undesirable signal problems. In order to achieve the desired higher level of integration, the technology must keep almost the same storage capacitance on a greatly reduced cell area.
Efforts to maintain or increase the storage capacitance in memory cells with greater packing densities have included the use of a stacked cylindrical capacitor design in which the capacitor cell uses the space over the device area for the capacitor plates. In U.S. Pat. No. 5,389,568 to Yun, the inventor describes a method of forming a cylindrical capacitor with a central pillar including a hole. U.S. Pat. No. 5,438,013 to Kim et al teaches a method of forming a double cylindrical capacitor. U.S. Pat. No. 5,364,809 to Kwon et al teaches a method of fabricating a multi-chamber type capacitor.